1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More specifically, the invention is in the field of fabrication of various layers related to HBT transistors in semiconductor devices.
2. Related Art
A technique often employed in the fabrication process for semiconductor devices involves creating an opening in a certain region of various layers or the substrate in the semiconductor device in order to deposit or grow other materials in the opening. For example, one of the steps in constructing a silicon germanium heterojunction bipolar transistor (xe2x80x9cSiGe HBTxe2x80x9d) requires opening a targeted region in a layer of oxide and growing a film of SiGe in the opening to serve as the transistor base. Conventional methods for creating such an opening have proven less than satisfactory.
FIG. 1 depicts structure 10 which is used to illustrate problems associated with depositing a relatively thick film over the semiconductor substrate and opening a certain region in the film. In this example, creation of an opening is needed so that SiGe can be grown in the opening to complete fabrication of an NPN HBT transistor. Certain details and features have been left out of FIG. 1 which are apparent to a person of ordinary skill in the art. Structure 10 includes components of a field effect transistor (xe2x80x9cFETxe2x80x9d), in this instance a P-channel field effect transistor (xe2x80x9cPFETxe2x80x9d), and a NPN HBT that are still under construction.
As seen in FIG. 1, structure 10 includes collector 12 for a SiGe NPN HBT. Collector 12 has top surface 14. Buried layer 16, which is composed of N+type material, is formed in silicon substrate 17 in a manner known in the art. Collector sinker 18, also composed of N+type material, is fonned by diffusion of heavily concentrated dopants from the surface of collector sinker 18 down to buried layer 16. Deep trench structures 22 and field oxide structures 24, 25, 26, and 28, composed of silicon dioxide (xe2x80x9cSiO2xe2x80x9d) material. are formed in a manner known in the art. Deep trench structures 22 and field oxide structures 24, 25, 26, and 28 provide electrical isolation from other devices on silicon substrate 17 in a manner known in the art.
Structure 10 of FIG. 1 also includes features and components of a CMOS device, such as a P-channel field effect transistor, or PFET, on the same wafer as the NPN HBT. Structure 10 includes N well 32 for a PFET. Structure 10 further includes source 34 and drain 35. Structure 10 also includes gate oxide 36 and gate 38, which in this example is polycrystalline silicon. Both gate oxide 36 and gate 38 are formed in a manner known in the art.
It is additionally seen in FIG. 1 that thick conformal layer 42 is deposited on the semiconductor surface, and additional conformal overcoat layer 44 is deposited on thick conformal layer 42. Conformal layer 42 can be a dielectric material known to those skilled in the art and may be, for example, SiO2 or silicon nitride. Overcoat layer 44 can consist of, for example, polycrystalline silicon. Opening 45 with width 48 is the result of an etching process that etches thick conformal layer 42 and overcoat layer 44 selectively down to top surface 14. Etching can be done by a method known in the art such as a hydrogen fluoride (xe2x80x9cHFxe2x80x9d) wet etch. Some problems with this approach are that HF is an isotropic etcher, i.e. it etches in all direections, and further a lengthy etch time is required to etch through thick conformal layer 42. These problems cause undercutting in thick conformal layer 42. These problems and the resulting undercutting they produce leave width 48 of opening 45 uncertain, and most often, larger than intended.
Continuing with FIG. 1, the uncertainty in size of width 48 of opening 45 create by the undercutting of thick conformal layer 42 means that any subsequent film deposited in opening 45 will be of indeterminate dimensions. An example would be the epitaxial growth of SiGe film 46 in opening 45 to serve as the base for an HBT. Undercuts 47 result in lack of control of critical physical dimensions in the SiGe HBT. such lack of control in turn results in undesirable electrical properties. For example, for certain applications, the base-collector parasitic capacitance can be undesirably increased. As another example, in certain applications control over precise dimensions of the SiGe HBT base can be impaired. Whenever there is imprecision in building the SiGe HBT. performance is compromised. Thus, when undercutting occurs from the etching step such that the dimensions of width 48 of opening 45 are uncertain the SiGe HBT will not perform optimally. Another problem caused by the undercutting is the difficulty in trying to implant, for example, dopants in certain regions of the deposited film that are obscured by the undercut.
Creating an opening in a relatively thin layer of material does not present the level of undercutting associated with creating an opening in a relatively thick layer. For example, when an opening is needed in a thin layer of a-dielectric film, the etch time necessary to etch through the relatively thin dielectric layer is comparatively brief, and the short etch time keeps undercutting to a minimum. Unfortunately, a different problem arises with thin layers. FIG. 2 shows the difficulties encountered with having to create an opening in a thin conformal film. Structure 20 of FIG. 2 is similar to structure 10 of FIG. 1 and has the same device components that make up structure 10 in FIG. 1. In addition, thin conformal film 52 is deposited over silicon substrate 17 and its various regions such as the field oxide regions. and forms a thin conformal film. Conformal overcoat 54 is deposited on thin conformal film 52. Opening 55 with width 58 has been etched through overcoat 54 and thin conformal film 52, down to top surface 14 in a manner known in the art.
The etch time necessary to etch through thin conformal film 52 is relatively short, and minimal undercutting occurs. The significant reduction in undercutting means that the dimensions of width 58 of opening 55 can be controlled with greater precision, and any subsequent material deposited in opening 55 will have dimensions that are better controlled. FIG. 2 further has SiGe film 56 grown over thin conformal layer 52 and conformal overcoat 54. It is seen that SiGe film 56 also grows in opening 55 where it assumes width 58. In the present example, control of the dimensions of the grown SiGe layer is critical to the performance of the HBT. Because undercutting of conformal layer 52 is minimal, the dimensions of SiGe film 56 grown in and close to opening 55 can be controlled much more precisely. When creating an opening in a relatively thin film, the uncertainty in the dimensions of subsequent materials deposited or grown in the opening created in a thick layer is avoided.
While creating an opening in thin conformal layer 52 causes minimal undercutting, FIG. 2 shows that other problems develop with this process. Because of the relative thinness of thin conformal film 52 where it deposits on gate 38, the subsequent depositing of conformal overcoat 54 at gate 38 produces a sharp edge or cusp at the upper coerners of gate 38. It is seen in FIG. 2 that the: growth of SiGe film 56 on gate 38 is non-conformal and produces a non-ideal property of deposition. This non-ideal property of deposition is also referred to as non-isotropic deposition. In the present example, the non-isotropic deposition of SiGe leads to a phenomenon called xe2x80x9cbreadloafingxe2x80x9d. Breadloafing occurs where the non-conformal film, in this case SiGe film 56, wraps around the sharp edges of conformal overcoat 54 at the upper corners of gate 38, and extends beyond the upper corners of gate 38, producing a profile resembling a slice of bread.
Continuing with FIG. 2, overhangs 57 characterize breadloafing and create crevices 51 beneath them and along the sidewalls of gate 38. Crevices 51 are the chief cause of problems associated with depositing material in an opening created in a relatively thin film. With overhangs 57 present, subsequent films deposited on SiGe film 56 can accumulate in crevices 51. When these subsequent films are removed in an etching step or other photolithography process, overhangs 57 function as a mask, preventing the etchant from reaching film materials trapped beneath. The materials trapped beneath overhangs 57 and in crevices 51 are thus unintentionally left behind and form what are termed xe2x80x9cstringersxe2x80x9d. FIG. 2 shows stringers 59 trapped beneath overhangs 57 and in crevices 51 following an etching step intended to remove all films deposited on SiGe film 56. Furthermore when it becomes necessary to etch the SiGe film 56 itself. these stringers micromask and prevent etching of the SiGe trapped beneath them.
The existence of stringers during semiconductor fabrication can detrimentally affect semiconductor performance. For instance, stringers are sometimes very conductive because the film material from which they are derived is conductive, and the presence of conductive material in unintended places can affect the electrical profile and function of nearby devices.
Thus it is seen that a method is needed that will improve the ability to open certain regions on the substrate surface for further fabrication of the semiconductor. More specifically, a method is needed that will permit creating openings without the undercutting or breadloafing produced by conventional methods and that will prevent the non-ideal deposition of subsequent films.
The present invention is directed to a method for opening a semiconductor region for fabricating a heterojunction bipolar transistor. The method of the present invention results in an improvement of the ability to open certain regions on the substrate surface for further fabrication of the semiconductor. More specifically, the invention""s method permits creating openings without the, undercutting or breadloafing produced by conventional methods and will aid in proper deposition of subsequent films.
According to the method of the present invention, a transistor gate is fabricated on a substrate. For example, the transistor gate can be a polycrystalline silicon gate in a FET. Thereafter, a conformal layer is deposited over the substrate and the transistor gate. For example, conformal layer can be any suitable dielectric such as silicon dioxide, silicon nitride, or a low-k dielectric. The conformal layer is then etched back so as to form spacers on the sides of the transistor gate. Subsequently, an underlying dielectric layer is formed on the substrate, the transistor gate, and the spacers on the transistor gate. The underlying dielectric layer can be, for example silicon dioxide or other suitable dielectric material such as silicon nitride or a low-k dielectric.
Next, an overcoat layer is fabricated on the underlying dielectric layer. The overcoat layer can be, for example, polycrystalline silicon. Once the overcoat layer has been formed, an opening is etched in the overcoat and underlying dielectric layers. Subsequent films can be deposited in the opening etched in the overcoat and underlying dielectric layers. For example, silicon germanium can be grown in the opening for the purpose of fabricating a silicon germanium heterojunction bipolar transistor.